Paper Special Issue on Novel Vlsi Processor Architecture Processor Pipeline Design for Fast Network Message Han- Dling in Rwc-1 Multiprocessor
نویسندگان
چکیده
In this paper we describe the pipeline design and enhanced hardware for fast message handling in a RICA-1 processor, a processing element (PE) in the RWC-1 multiprocessor. The RWC-1 is based on the reduced inter-processor communication architecture (RICA), in which communications are combined with computation in the processor pipeline. The pipeline is enhanced with hardware mechanisms to support ne-grain parallel execution. The data paths of the RICA-1 super-scalar processor are commonly used for communication as well as instruction execution to minimize its implementation cost. A 128-PE system has been built on January 1998, and it is currently used for hardware debugging, software development and performance evaluation. key words: massively parallel computer, loosely coupled multiprocessor, multi-thread execution, super-scalar processor, processor pipeline
منابع مشابه
MIPS: A VLSI Processor Architecture
MIPS is a new single chip VLSI processor architecture. it attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used. .
متن کاملOrganization and Vlsi Implementation of Mips
MlPS is an 32-bit, high pcrformancc processor architecture implcmcntcd as an nMOS VLSI Gp. I'hc processor uses a low 1~~1, strcamlincd instruction set coupled \vit!l a fast pipeline to achicvc an instruction rate of two million instructions per second. Close interaction bctwccn the processor dcsigll and car-npilzrs for the machine yields cfficicnt execution of programs on the chip. Simplifyin g...
متن کاملA Large Scale Image Processing System TIP-4 Prototype
data flow VLSI processor ImPPs( Image Pipelined Processor :pPD7281). lmPP capable of performing 5 million instructions per second(5 MIPS), so TIP-4 has maximum processing speed of 2560 million instructions per second(2. 5GIPS) The prototype system TIP-4P that has actually been developed has 64 ImPPs, thus the peak computation rate for TIP-4P is 320 MIPS. To use 512 ImPPs efficiently. TIP-4 has ...
متن کاملProcessor Design Issues for Parallel Machines
This paper addresses processor design issues for multiprocessor architectures. We assert that some architectural features desirable for a uniprocessor are not as eeective in a multiprocessor. Issues aaecting processor design include granularity, degree of parallelism, cache and network eeects, and dynamic load balancing. We show that using single-instruction-issue processor with dynamic instruc...
متن کاملSingular value decomposition on processor arrays with a pipelined bus system
Singular value decomposition (SVD) is used in many applications such as real-time signal processing where fast computation of these problems is needed. In this paper, parallel algorithms for solving the singular value decomposition problem are discussed. The algorithms are designed for optically interconnected multiprocessor systems where pipelined optical buses are used to connect processors. ...
متن کامل